This application claims the priority of Korean Patent Application No. 2003-73637, filed on Oct. 22, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a recess channel array transistor (RCAT) used for a highly integrated semiconductor circuit.
2. Description of the Related Art
Lengths of channels are being shortened as a result of high packing density in semiconductor devices such as DRAMs, causing short channel effect and punchthrough between source and drain regions, of which influences are hardly controlled. Particularly, design rules are gradually decreased to result in short channel effect and increased amount of ion implantation, which in turn increases a leakage current. Therefore, it is difficult to secure a refresh time of a DRAM. Recess channel array transistors are MOSFET devices suggested for solving the foregoing problems. In order to overcome the problems caused by the decreased lengths of channels due to the shrinkage of the devices, a recess channel array transistor is suggested, which is a semiconductor device capable of securing a sufficiently increased channel length by forming a recess channel trench in a portion where a channel of the transistor is formed later.
FIG. 1 is a sectional view showing a structure of a conventional recess channel array transistor.
Referring to FIG. 1, a recess channel trench 130 is formed in a semiconductor substrate 100 that is formed with a field ion implanting region 105, an ion-implanted impurity region 115, and source/drain regions 180. A gate oxide layer 135 is formed along an inner wall of the recess channel trench 130. Also, a gate stack 165 formed of sequentially stacking a gate polysilicon layer 140a, a gate metal layer 150a and a capping layer 160a is formed on the gate oxide layer 135, thereby thoroughly filling the recess channel trench 130. Sidewalls of the gate stack 165 are formed with spacers 170, and contact pads 190a, 190b and 195 self-aligned using the spacers 170 are formed on insides an interlayer insulating layers 185. A reference numeral 110 denotes a shallow trench isolation (STI) layer that defines an active region. The recess channel array transistor constructed as above has a channel formed along an outer periphery of the recess channel trench 130. Accordingly, the length of the channel becomes longer than that of a planar type transistor. Therefore, punchthrough between the source and drain can be minimized.
However, according to the method of fabricating the conventional recess channel transistor, a process of forming a recess channel trench is added. Thus, a misalignment margin is trivial when an active region pattern is formed, a recess channel trench pattern, a gate pattern and a self aligned contact (SAC), so that photolithography of forming the patterns becomes fastidious. In other words, the recess channel trench pattern has no misalignment margin with not only the active region but also a gate, thereby making the process complicated and fastidious. Japanese Patent Laid-open No. 2002-353445 discloses a method of fabricating a recess channel transistor in an active region isolated by a STI.
FIGS. 2a through 2e are sectional views showing a method of fabricating a conventional recess channel array transistor.
Referring to FIG. 2a, after an ion implanting region 105 is formed in a semiconductor substrate 100, an isolating layer 110 such as STI is formed for defining an active region. By source/drain ion implanting to a surface of the semiconductor substrate 100, a surface ion-implanted source/drain impurity region 115 is formed. Then, a mask pattern of a photoresist layer 125 that opens portions to be formed with recess channel trenches is formed on the semiconductor substrate 100. When a highly narrow recess channel trench is intended, a hard mask layer such as a silicon nitride layer may be used instead of using the photoresist layer.
Referring to FIG. 2b, the semiconductor substrate 100 is etched using the photoresist layer 125 as an etch mask, thereby forming a recess channel trench 130. As shown in FIG. 2c, a gate oxide layer 135 is formed on a surface of the recess channel trench 130. Then, a conductive polysilicon 140, a metal 150 such as WSi, and an insulating material 160 such as silicon nitride for a capping layer are sequentially stacked on the gate oxide layer 135.
As shown in FIG. 2d, the insulating material 160 for the capping layer, the gate metal 150 and the conductive polysilicon 140 are patterned, so that a gate stack 165 formed of a capping layer 160a, a gate metal layer 150a and a gate polysilicon layer 140a is formed. Spacers 170 formed of silicon nitride are formed along sidewalls of the gate stack 165. Thereafter, the spacers 170 and the capping layer 160a are used as masks during performing the source/drain ion implantation, thereby forming source/drain 180 in the semiconductor substrate 100.
Referring to FIG. 2e, an interlayer insulating layer 185 is formed on the entire surface of the resultant structure, and a portion of the interlayer insulating layer 185 in which a contact is formed later is selectively removed via photolithography and etching, forming a contact hole. Conductive polysilicon is then deposited to fill the contact hole and planarized via chemical mechanical polishing (CMP), thereby forming self-aligned contact pads 190a, 190b and 195. By doing so, a recess channel array transistor is fabricated. If the recess channel array transistor fabricated as above is used as a cell transistor of a DRAM cell, the self-aligned contact pads 190a, 190b and 195 are electrically connected to a lower electrode or a bit line (not shown) of a cell capacitor, respectively.
In the method of fabricating the conventional recess channel array transistor as described above, an added process of forming a recess channel trench requires an additional photolithography step. Thus, photolithography is repeated four times to fabricate the recess channel array transistor. To summarize, photolithography is used to form 1) an active region pattern using the STI, 2) a recess channel trench pattern, 3) a gate pattern, and 4) a self-aligned contact (or self-aligned contact pads) pattern. Accordingly, a decreasing design rule of a semiconductor device results in a decreased misalignment margin between the recess channel trench pattern and the active region, as well as a decreased misalignment margin between the recess channel trench pattern and the gate pattern. As a result, the fabricating process of the recess channel array transistor is complicated, and a short can occur due to misalignment.
For example, if an undesired trench is formed in an isolating layer of a field region caused by the misalignment between the recess channel trench and the active region, an operation of the transistor may fail. Also, when the misalignment between the recess channel trench and the gate inhibits precise formation of the gate on the recess channel trench, the gate may be shorted with a neighboring contact pad (e.g., the contact pad 195 connected to the bit line).
Therefore, it is desirable to know and use a method of fabricating a recess channel array transistor capable of sufficiently securing a misalignment margin between the recess channel trench, the active region, the gate and the self-aligned contact.